use of the real-time operating systems upon which much embedded software is based. ln . schematic example at the end of Chapter 3 and who ran down a legible copy of it. Finally . You are free to use ¿LC/OS as a study tool, but you may. About This Book and the Accom. A First Look at Embedd. Examples of Embedded Syste । Typical Hardware 8 ;. Chapter Summary Hardware. David bvifacts.info: “An Embedded Software Primer”, Pearson Education, 2. Reference Books: and design by Rajkamal, TMH. Download more ebooks.
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An Embedded Software Primer - Ebook download as PDF File .pdf), Text File . txt) or You are free to use pC/OS as a study tool, but you may not use it for a. Getting the books an embedded software primer now is not type of inspiring means. Language: English ISBN ISBN eBook. second edition, instrumentation engineers handbook free download, livro. easy to read. --David Cuka An Embedded Software Primer is a clearly written. a Kindle? Get your Kindle here, or download a FREE Kindle Reading App.
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Unlike open-collector devices, tri-state devices canand will have bus fights ifone of them tries to drive J signal low and another tries simultaneously to drive that signal high. Tri-state devices can overheat and burn up in bus fights just like regular parts. If the software controls the select signals in Figure 2. If hardware controls them, then the hardware engineer must ensure this.
Examine the circuit in Figure 2. The problem is that the output signal from the inverter in the lower left corner of the figure is connected to the input signals of an awful lot of other parts. This is the loading problem. Manufacturers provide data about each part that indicates how much current it em drive out of its outputs and how much current is required for its inputs. I Lrdware must ensure that the outputs driving each signal in the crrcurr can generate enough current to make all of the inputs happy.
As a software engineer, you should not have to worry about this problem, but you'll occasionally see peculiar things on the schematics of your systems that will turn out to be solutions to this problem. It is useful to be familiar with the common. The driver essentially boosts the signal. The only potential difficulty with this solution is that the driver invariably introduces at least a little delay into the signal.
In the figure you can see that whenever one of the inputs goes low, the output goes high just a little later. In a real timing diagram from a chip manufacturer. This amount of time is called the propagation delay. For a NAND gate, that time would be just a few nanoseconds, but part of the hardware engineer's job is to make sure that the nanoseconds don't add up to a signal arriving late at its destination.
So far, all of the parts that we have discussed have depended only upon the levels of the input signals, that is, whether those signals are high or low. Other parts depend upon edges in the signals--tre transitions of the signals from high to low and vice versa.
The transition of a signal from low to high is called a rising edge. The transition of a signal from high to low is called a falling edge. In Figure 2. Nothing happens instantaneously in the world of digital circuits, and one of the tools that parts manufacturers lise to communicate the characteristics of the parts to engineers is a timing diagram. A tillg diagram is a graph that shows the passage. Although NAND gates are so simple that manufacturers don't normally publish.
The timing diagram for a D flip-flop indicates the minimum required for these two times probably just a few nanoseconds. The timing diagram also indicates the maximum amount of time, called the clockto-Q time, after the rising edge of CLK before the Q output is guaranteed to be valid.
Sometimes this amount of time is different, depending upon whether Q is going high or going low, Note that the terms setup time, hold time, and clock-to-Q time are used tor all kinds of parts, even for parts with no signal caned Q.
In the timing diagram in Figure 2. Timing diagrams often use this convention. Note also that Figure 2. A D flip-flop is essentially a I-bit memory. A similar part, caned a latch, also can be used as a memory. A latch is the same as a D flip-flop in that it captures the state of the D input on the rising edge of the CLK input.
However, the Q output in a latch is driven to be the same as the D input whenever the CLK input is low, whereas the Q output in a D flip-flop does not change until the rising edge of the CLK input.
D flip-flops have more interesting timing diagrams, because the timing relationship between the two inputs is critical. However, there is a minimum amount of time, both before and after the rising edge of the eLK signal, during which the D input must remain constant for the D flip-flop to run reliably.
The time before the rising edge of cue during which the D input mustremain constant is called the setup time. IS that it is often desirable to have the clock signal freSllency be an integer multiple of the data rate on your network or serial port or other communications medium.
It's a lot easier to divide the clock signal by an integer to create another signal at the correct data rate than it is to divide by some fraction. It's even easier to divide by some power of two. Each will have a setup time, a hold time, and a clock-to-Q time, but for clarity some of the tunes arc shown on one cycle and some on the other.
This is also a common timing diagram convention. In this section, we'll discuss the memory parts typically found in an embeddedsystem circuit. Memories of' all kinds are sold in a variety of widths, sizes, and speeds. For example, a "8 x KB 70 nanosecond memory" is one that has KB3 storage locations of 8 bits each that can respond to requests for data within 70 nanoseconds.
After you decide what kind of memory is useful for your system, you buy the size and speed that you need. Obviously, for a circuit to do anything interesting, the levels on the signals have to change, Some embedded-system products do tbings only when external events cause a change Or!
For example, a microprocessor.. To accomplish this, most circuits have a signal caned the clock. The timing diagram for the clock is very simple and is shown in Figure 2. The purpose of the clock signal is to provide rising and falling edges to make other parts of the circuit do their jobs.
The two types of parts used to generate clock signals are oscillators and crystals. An oscillator is a pare that generates a dock signal an by itself Oscillators typically come in metallic packages with four pms: A crystal has just two signal connections, and you must build a little circuit around it to get a clock signal out.
Many microprocessors have two pins on them for attachment to a circuit containing a. You can buy oscillators and crystals 1Il a wide range offrequencies. In picking a frequencv consider first that since other parts in the circuit must react to the clock signal, the clock signal must be slow enough that the other parts' timing requirements are met.
For example, when you buv a microprocessor that is the 'megahertz model, this means that that microprocessor will work with a clock signal that is 16 megahertz. Note, however, that microprocessors frequently need a crystal that oscillates at some multiple. Almost every computer system needs a memory area in which to store the instructions of its program.
This must be a nonvolatile memory, that is, one that does not forget its data when the power is turned off In most embedded systems, which do not have a disk drive or other storage medium, the entire program must be in that memory, In a desktop system, enough program must be in memory to start up the processor and read the rest of the program from a disk or a network. Most computer systems use some variant of Read-Only Memory, or ROM pronounced "rahm," just like you would expect for this purpose.
The characteristics of ROM are the following. This timing diagram illustrates several other conventions often used in timing diagrams. With parts such as memory chips, which have multiple address or data signals, it is common to show a group of such rel: With such a group of signals, a single line that is neither high nor low indicates that the signals are floating or changing.
When signals take on a particular value, that is shown in the timing diagram with two lines, one high and one low, to indicate that each of the signals has been driven either high or low. The Humber of these depends upon the size of tbeRC! There are typically eigbt or sixteen of these. It is sometimes called the chip select signal. The read enable signal is often called output enable, or OEI, instead. Although it may seem redundant, it is normal for ROM parts to have both a chip enable signal and a read enable signal.
The purpose for this will become apparent in the next chapter, when we discuss bus architectures.. Note that it is very common forthcse enable signals to be asserted low. I At about the same time, the chip enable signal is asserted, m A little while later the microprocessor asserts the read line. The typical critical times for a ROM chip are the tollowmg:. How long is It between the time when the address is valid and the chip enable signal IS asserted and the time when the data signals driven by the ROM are valid'.
OMs are. It takes a m. If a program in a PROM has a mistake. The usual way to erase an EPROM is to shine a stronz ultraviolet hght mto a window on the top of the chip. However, there are a few limitations of flash memory that you should know about:.
You can write new data into flash memory only a certain number of times before it wears out, typically on the order of 10, til11es4.
In most flash memories you have to write a whole block of data, say bytes or maybe even 4K bytes, at one time. There is no way to write just 1 byte or 4 bytes.
The writing process is very slow unlike the reading process, which is fast , taking on the. The microprocessor usually can't fetch instructions from flash during the several milliseconds that it takes to write new data into the flash. Therefore, the flashprogramming program itself has to be stored somewhere else, at least when it is actually running.
For these reasons, the most typical use of flash memory is to store a program or rarely changed configuration data such as all IP address or the date on which the product should next be serviced and the diagnostic-programs run. EEROM is very. In fact, some EEROMs require that you write a little software routine to get data into and out of them one bit at a time. I You can write new data into an EEROM only a certain number of times before it wears out, but that number is often on the order of millions of times, so in many applications the limit doesn't matter.
It is used instead to store configuration information that might change relatively. All of the quantitative characteristics mentioned in this book about memory parts were current when the book was wr itren. However; as this is an area of rapid development and evolution, you should assume that they may have changed by now,. Table 2. ROM is useful for programs.
It is programmed at the semiconductor factory. After an initial setup charge, ROMs are the least expensive type of permanent memory, and they are thus the best choice for a product with large volumes. In general, although they are not quite as fast as RAMs, ROMs are still fast enough to allow most microprocessors to execute programs directly from them. It can be erased by shining a strong ultraviolet light on it for 10 or 20 minutes and then reused; it is therefore useful when you are debugging a program.
Flash is useful for storing programs. The principal advantage of flash over the various other kinds of program memory is that it can be written to even after the product is shipped; for example, to upgrade to a new software version. Since it cannot be written to quickly, however, it is unsuitable for rapidly changing data.
EEROM is useful for storing data that must be remembered when the power goes off. Also, some very fast microprocessors would be slowed down if they executed the program directly from any flavor of ROM; in these cases, it is sometimes useful to copy the program from ROM to RAM at power-up time. Every computer system needs a memory area in which to store the data on which it is working. The general characteristics of RAM are. I Decoupling capacitors prevent local brownouts in a circuit.
Open collector devices can frive their outputs low or let them float but they cannot drive them high. You can connect multiple open collector outputs to the same signal; that signal will be low ifany output is driving low,.
You can connect multiple tri-state OUtputs to the same signal, but you must ensure that only one of the outputs is driving the signal at anyone time and that the rest are letting the signal Boat.
I A single output can drive only a limited number of inputs. Too m;my inputs leads to an overloaded signal. AMas it docs so. Statlc RAM remembers its data without any assistance from other parts of the rircuit. Dynamic RAM, on the other hand, depends on being read once llJ a while; otherwise, it forgets its data, To solve this problem, systems employing dynamic RAM use a circuit-v-oficn built into the microprocessor-ecalled dynamic RAM refresh, whose sole purpose 1S to read data from the dynamic RAM periodically to make sure that the data stays valid.
This may seem like: A'vl is comparatively cheap. Static RAM perm look much like ROM parts, except that they have a write enable signal in addition to the other signals, which tells the RAM when it should store new data, Dynamic RAM is morecomplex and is quite different; a discussion of how circuits containing dynamic RAM must be built is beyond the scope of [his book,.
Since they each have unique characteristics, YOLl will use them for different things,. I Ivlost semiconductor parts, chips, are sold in plastic or ceramic packages. They are connected to one another by being soldered to printed circuit boards. Elcru iral engineers draw schematic diagrams to indicate what parts are needed in each circuit and how they are to be connected to one another.
Names are often assigned to signals on schematics,. A signal is said to be asserted when the condition that it signals is true. Some signals are asserted when they are high; others, when they are low. In most cases, each signal must be driven by exactly one output, although it can be connected to multiple inputs.
How would you expect to see that circuit really appear on a schematic? The idea is that the circuitry on the lefthand side is always running, but the circuitry on the right-hand side gets turned on and offfrom time to time to save power. The capacitor shown in the middle of the diagram is intended to cushion the voltage when the switch is closed. What is wrong with this design? What will the symptoms most likely be? How should it be fixed? Why does the circuit in Figure 2.
How does the circuit in Figure 2. What does the timing diagram for a static RAM look like? Remember to include both a read cycle and a write cycle. Microprocessors come in all varieties from the very simple to the very complex, but in the fundamental operations that they perform. In this section, we will discuss a very basic microprocessor, so basic that no one makes one quite this simple. However, it shares characteristics with every other microprocessor.
It 1las the following signals, as shown in Figure 3.
I A collection of data signals it uses to get data from and send data to other pans in the circuit. II A clock signal input, whir h paces all of the work that the microprocessor docs and, as a consequence. Most microprocessors have many more signals than this, and we'll discuss some of them later in the chapter.
However, the above collection is all that the microprocessor needs in order to fetch and execute instructions and to save and rerrieve data. SCHne people use the term microcontroller for the very small end of the range of available microprocessors. Although there is no generally accepted definition for rnicrocontrolkr, most people use it to mean a small, slow microprocessor with some RAM and some ROM built in, limited or no capability for using RAM and ROM other than what is built in, and a collection of pins that can be set high or low or sensed directly by the.
Since the principles of programming a microcontroller are the same as those for programming 3 microprocessor, and since manufacturers build these parts with every combination of capabilities imaginable; in this book we will use the term microprocessor to rnean both. Similarly, the data signals are often referred to as the data bus. The schematic in Figure 3. Itjust has a 64 K address space, and when it drives address on the address bus to represent one of the addresses in this address sp.
Then voumust build circuitrvtojmplemcnr your division. Y U can do the arithmetic and see rhatborhof the ranges in Table 3. As an example, consider what happens if the microprocessor tries to read from address Ox The A15 signal will be a 1 because Ox is in binary , which means that the chip enable signal on the ROM will be high, and the ROM will therefore be disabled.
But because the A15 signal is high, the output of the inverter at the bottom of Figure 3. See Figure 3. Figure 3. In this particular case this is simple.
Notice that 1Il all of the addresses that correspond to ROM, the highest-order address signal A15 IS 0, whereas in all of the addresses that correspond. AM-should be activated. In Figure 3.
Some microprocessors allow an alternative mechanism because they support two address spa cs: TillS enables the memory 1ll the memory address space in the range. Note that since this circuit asserts DVl's chip enable signal whenever A1 ' and TlO are high and docs not check A18 through AS, the circuit can read from or write to DVl no matter what the values of those address Effectively, whatever the circuit reads from Ox O, it can also read from Ox, Ox, Ox8feOO, and so on, Similarly, the same data dppears at.
In addition to the logic problems of hooking up the address and data busses correctly in figure 3,2, another issue that must be resolved j" the problem of timing. For the circuit to work, the signals that the microprocessor produces must conform to the requirements of the other parts in the circuit.
The various mechanisms by which this can be accomplished arc referred to collectively as bus handshaking, Several of these mechanisms are discussed below, One of them requires the active cooperation of the software,.
As long as the WAIT signal is asserted, the microprocessor will wait indefinitely for the device to put the data on the bus. This is illustrated in the lower half of the figure. The only disadvantage of using a WAIT signal is that ROMs and RAMs don't come from the manufacturer with a wait signal, so someone has to build the circuitry to drive the wait signal correctly, and this can take up engineering time to design and cost money to build. Some microprocessors offer a third alternative for dealing with slower memory devices-wait states.
To undcrstand wait states, you need first to understand how the microprocessor times the signals on the bus in the first place.
The microprocessor has a clock input, as we've mentioned. Examine Figure 3. Each of the signal changes during the bus cycle happens at a certain time in relation to the microprocessor's input clock signal. The clock cycles in a single bus cycle are typically labeled T1, T2, T3, etc. The microprocessor shown in this figure behaves as follows This is essentially the timing of a Zilog Z I It outputs the address on the rising edge of 1'1; that is, when the clock signal transitions from low to high in the first clock cycle of the bus cycle.
Ii It expects the data to be valid and actually takes the data in just a little after the rising edge ofT3 shown by the third vertical line in the figure. The next clock cycle would be T1 of the following bus cycle, and if the microprocessor is ready, It will drive another address onto the address bus to start another bus cycle.
If this microprocessor is capable of using wait states, then it will be able to insert extra clock cycles, typically between cycles T2 and T3. However, the microprocessor then waits one extra bus cycle before reading the data and completing the cycle.
A piece of circuitry inside the microprocessor called a wait state generator is responsible for this behavior. Most wait state generators allow software to tell them how many wait states to insert into each bus cycle, up to some maximum, perhaps thee or perhaps fifteen. Most microprocessors also allow you to use different numbers of wait states for different parts of the address space. This latter is useful because some devices are much faster than others: The typical microprocessor inserts the maximum number of wait states into every bus cycle when it is first powered up or is reset.
This means that the hardware engineer can use a slow ROM ifhe or she wants to save some money. It also means that the processor will start off very slowly, even if the hardware engineer decides to pay for a fast ROM. It is obvious that the fewer wait states that your system is using the faster it will run. It is up to software engineers to find out from the hardware engineers how few wait states they can get away with, and then write code to set up the wait state generator accordingly.
One way to get data into and out of systems quickly is to use direct memory access or DMA. However, DMA creates some new problems for hardware designers to resolve. The first difficulty is that the memory only has one set of address and data signals, and DIV1A must make sure that it is not trying to drive those signals at the same time as the microprocessor is trying to drive them.
This is usually solved in a manner similar to that shown in Figure 3. Note that Figure 3,9 includes two new timing diagram conventions. First, the cross-hatching in the address and data buses indicates that the circuit we are discussing does not care what the values are and that those buses may be driven by other components during that time.
When the cross-hatching ends, it indicates that the other circuits should stop driving those signals. Second, the arrows indicate which edges cause which subsequent edges. One question that must.
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The advantage of this second architecture over the one shown in Figure 3. The lIO device needs only to be able to assert DMAREQ at appropriate nmes, because the fulfillment of the request looks like a regular read from the perspective of the 1I0 device.
On the other hand. I It takes about twice as much bus time to transfer the data. As you probably know. The signal that tells the microprocessor that it is time to run the interrupt routine is the interrupt request or IRQ. Most microprocessors have several external interrupt request input pins on them.
See the schematic in Figure 3. At the bottom of the UART is a connection into a clock circuit.
fermentist.no has expired
The clock circuit for the UART is often separate from the microprocessor's clock circuit, because it must run at a frequency that is a multiple of the common bit rates. UART clock circuits typically run at odd rates such as There is no similar restriction on the clock that drives the microprocessor. The signals on the right are the ones that go to the serial port: The UART usually runs at the standard 3 or 5 volts of the.
Its purpose is to convert data to and from a serial interface, that is, an interface on which the bits that make up the data are sent one after another. A veri common standard tor serial interfaces is the RS interface, used between computers and modems and nowadays often between cOlnputers and mice. A tvpical Uo. RT and its connections are shown in Figure 3. On the lefthand side of the UART are those signals that attach to the bus structures we discussed back in Section 3.
A typical DART, in common with many other L'O devices, has a handful of internal locations for data, usually called registers, to which the microprocessor can write to control behavior of the UART and to send it data to be transmitted and from which the microprocessor can read to retrieve data that the UART has received.
Each register is at a different address within the UART. The typical registers you might fmd in a UART include the following:. The microprocessor writes the data a byte at a time, and the UART will transmit them a bit at a tirnc.
Note that this might be at the same address within the UART as the previous register, since the manufacturer of the UART can reasonably assume that you will on lv read from this register and only write to the other. Note that it is often the case that you cannot read back data that you have written into registers in UARTs and other devices, whether or not the manufacturer has used the same address for another register.
A register with a collection of bits that indicate any error conditions on received characters bad parity, had framing, etc. Individual bits that register might indicate that the UART should interrupt when it has received a data byte, when it has sent a byte, when the clear-to-send signal has changed on the port, etc. Note that rcad1l1g or writing this or other registers in the UART often has side effects.
Typically, Ul'l. RTs can divide their clocks by whatever number you specify.
Your program controls the UART by reading from and writing to these registers'at appropriate moments. The UART will store the bytes and eventually catch up. I Similarly, re complex UARTs contain FIFOs for data that is being received, relieving your software of the requirement to read one byte before the next one arrives. Most systems require a certain amount of glue circuitry in addition to the microprocessor, the ROM, the RA.
M, and the other major parts. Glue circuitry connects outputs that assert high to inputs that assert low, drives chip-enable signals appropriately based on the address signals, and so on. However, circuits with fewer parts are generally cheaper to build and more reliable, so engineers nowadays try to avoid large collections of these simple parts and use instead fewer, more complex parts. Each system needs its own combination of glue circuitry to work, however, so each one must be designed afresh.
No single chip will do the job for any arbitrary system. These devices allow you to build more or less any small glue circuit you want, even if what you want includes three-input NAND gates in which two of the inputs are inverted.
In essence, a PAL has a rather large collection of discrete parts in it and a method by which you can rearrange the connections among these parts and between the parts and the pins. PROM programmer. The ROM is at addresses 0 to Ox3ar; therefore, the glue must assert its chip enable signal when address lines 14 and 15 are both low. The RAM is at addresses Ox to Oxffif; therefore, the glue must assert its chip enable signal when address line 15 is high.
If we build this system with a PAL, the schematic might look something like the one in Figure 3. A 15, and the processor clock and generates the various chip enables and the WAIT signal back to the processor. Obviously, it's a little difficult to determine how the circuit in Figure 3.
The PAL equations can be written in any of several languages that have been created for the purpose.
An Embedded Software Primer
An example is in Figure 3. An exclamation point on the pin drcl. Note that because the pin declaration for the Ramee signal indicates that it is asserted when it i'; low, pin 19 of the PA L will go low and select the RAM whenever the microprocessor selects an address the range from Ox8C to Oxmf.
The equations for Wa it and Wa i t2 are a little different from those for the chip enable lines. The equations for the chip enable lines arc combinatorial. They depend only 11pOll the levels of the signals on the right-hand sides of the equation, and the output signals named on the left-hand sides of the equations change as soon as the input signals on the right-hand SIde change. The equations for ,ia i t and Wa i t2 are docked. The equations are only evaluated by the PALand the Wa i t and Wa i t2 outputs are only changed-e-on the edge of the given clock signal.
The difference between the two types of equations 1S shown this PAL equation language by the use of the colon: On the second rising edge of i C1 k, Wait will remain asserted because none of the signals on the righthand SIde of the equation will have changed , but now Wai t. On the third rising edge of t C'l k, WaH and Wait2 will both go low,. Note how Wait and Wait2 react only when iC1 k. Wait and Wait2 will he low nr first. See how these equations work:.
They allow the programmer to put a sequence of test vectors into the program, a sequence of inputs and a sequence of expected outputs. The device that prognl11s the PAL uses these vectors to ensure that the PAL operates correctly after it is programmed. An FPCA is like a iarge PAL, in that it has a large number of gates in it, and the connections among them can be programmed after the part has been manufactured. Some of these parts are programmed ill a special programming device; others can be programmed by the microprocessor even after the product has been shipped into the field.
In some systems, the software must program the FPGAs every time the system starts up. The watchdog timer has an output that pulses should the ever expire, but the idea is that the timer will never expire. Some mechanism allows software to restart the timer whenever it wishes, forcing the timer to start timing its interval over again. If the tuner is ever allowed to expire, the presumption is that the software failed to restart it often enough because the software has crashed.
Different watchdog cucuits require different patterns ofsignals on their inputs to restart them; typical is to require any edge on the RESTART signal. The timer circuit also may be able to function as a counter that counts pulses onthat input pin. Most timers are set up by writing values into a small collection of registers, typically registers to hold the count and a register with a collection of bits to enable the counter, to reset the interrupt, to control what the timer does to its output pin, if any, and so on.
It is not unusual to find a few DMA channels built into a microprocessor chip. Since a DMA channel and the microprocessor contend for the bus, certain processes arc simplified if the DIvlA channel and the microprocessor arc on the same chip. If your microprocessor supports some kind of memory mapping, note that the DMA circuitry will most likely bypass it.
DMA circuits operate exclusively on the physical memory addresses seen outside of the microprocessor chip. Microprocessors, particularly those marketed for embedded systerns, very often come WIth a number of auxiliary circuits built into them. In this section we'll discuss some of them.
An Embedded Software Primer
These auxiliary circuits are usually logically separate from the microproccssor-vthcv're just huilt on the same piece of silicon and then wired directly to the microprocessor. The advantage of these built-ins IS that you get the aux. These pins can be configured as outputs that software can set high or low directly, usually by writing to a register, or they can be configured as inputs that software can read, again usually by reading from a register. These pinS can be used for any number of purposes, including the following:.
It is commou for microprocessors to have one or more timers, A timer is essentially just a counter that counts the number of microprocessor clock cycles and then causes an mn-rrupt when the count expIres. I The timer can drive all output pIll on the microprocessor, either causing a pulse whenever the timer expires ot creating a square wave with an edge at every timer expiration.
As we have seen in some of our earlier discussions, using an address to generate chip enables for the RAM, ROM, and various peripheral chips can be a nuisance. Some microprocessors offer to do some of that address decoding.
Set Computer systems, contain a memory cache or cache on the same chip with the microprocessor. These are small, but extremely fast memories that the microprocessor USeS to speed up its work. The lIncroproceslor endeavors to keep in its cache the data and Instructions it about to need; microprocessor can fetch items that happen to be in the cache when. A15 IS that same address signal. I The actual pin numbers on the p.
Figure 3,20 is the schematic diagram fin d board distributed by ZiJog, to demonstrate its Z80 microprocessor and a cornmunicarion chip called duc sec, which is almost too fancy to be called a UART. A few comments. With this and with the. The labeled PI through 1'4 are indeed connectors, as you might expect. Since this IS a demonstration board. On most circuits you would not see so many signals going to connectors. The part labeled P5. J 3 and J 4 control how certain address lines connect to mernorv parts.
To start with you should assume that pin 2 and pin 3 on J3 have been connected to one another and that pin 2 and pin 3 OIl J4 have been connected to one another.
The part labeled 1'6 is also a connector, but its purpose. Assume that the user has connected none of these pins to one another. Because of the extensive configurabilitvof this board, many have pullup resistors attached to them. This forces them to be high if the user not [ lrCe them low. For example, the signal USRRAM, found on connector P6 and attached to one of the inputs on one of the NAND gates in the lower lcfthand corner of the schematic, will always be high because of the pullup resistor, unless the user connects it directly to ground by connecting pm 1 to pin 6 of connector P6.
I The part labeled US is a programmable logic device that deals with the timing requirements of the sec.
One thmg thatyou will notice whenever you talk to hardware engineers is that they operate with a different set of concerns than do software engineers. Here are some of those concerns:. Unlike software, for which the engineering cost is almost all of the cost, every copy ofthe hardware costs money. You have to pay for every part all the circuit every tune you build a new circuit.
Every additional part takes up additional space in the circuit. As companies start to build computers that are not only portable but also are wearable or even concealable, space is often at a premium. This is an obvious concern if your product is battery-powered, but even if it is not, more power means that your product will need a larger and therefore more expensive power supply.
Every additional part turns the power it uses into heat. Eventually you have to put a bigger fan into your product to get rid of this heat-or, worse, you have to turn a fan-less product into one with a fan. Faster circuit components cost more, use Ire power, and generate more heat.
Therefore, clever software is often a much better way to make a product fast than IS faster hardware. Because of these considerations, hardware engineers arc inclined to suggest that product functionality is best done in software rather than in additional hardware.
Prototypes and other very low volume products for which the software development cost will be a major portion of the total cost are the exceptions to this rule. I The electrical engineer must ensure that the timing requirements of each of the parts attached to the bus are satisfied. Wait states and wait lines are mechanisms for accomplishing this. UARTs are controlled by the microprocessor through a collection of registers.
A PAL contains a collection of gates; you can rearrange the connections among these gates with a special programming language and a PAL programmer. I A watchdog timer resets the microprocessor and starts the software over from the beginning if the software does not restart it pcriodically.
I In addition to making their circuits work, hardware engineers must deal with concerns about cost, power, and heat. Suppose that your system has two ROM chips and two RAM chips whose sizes and addresses are as shown in the following table.
Design the part of the circuit that takes the address lines and produces the chip enable signals for each of these.
Suppose we are using nanosecond ROMs which have valid data on the bus nanoseconds after the falling edge ofOE! Note that this. AM to ground by connecting pin 6 to pin lOll ,"lllle'nor Ph'. Having completed our digression into hardware, let's get started with our main subject-vernbedded-sysrem softwarc--starting with the response problem raised in Chapter 1. As discussed in that chapter, the respODse problem IS the difficult one ofmakmg sure that the embedded system reacts rapidlv to external events, even If it is in the middle of doing something else.
For example, even if the underground tank monitoring system is busy calculating how much gasoline is in tank number six, it must still respond promptly if rh- user presses a button. The first approach to the response problcrn-v-rhc Oile that we will discuss in this chapter-is to use interrupts. Interrupts cause the microprocessor in the embedded system to suspend doing whatever it is doing and to execute some different code instead, code that will respond to whatever event caused the inu-rrupt.
Interrupts can solve the response problem, but not without some difficult progr. Before we c. If you arc reas lLlbly familiar wirh.
Here we arc going to dlscllSs the little bit about microprocessor architecture and assembly language that you need III order to grasp some of the concepts. We're going to discuss the parts that are similar; we have no need for the details that make microprocessors and assembly languages complicated and make them differ from one another. A program called an assembler translates the assembly language into binary numbers before the microprocessor can execute them.
I When the compiler translates C, most statements become multiple instructions for the microprocessor to execute. Most C compilers will produce a listing file that shows the assembly language that would be equivalent to the C. I Every family of microprocessors has 3 different assembly language, because each family understand, a different set of instructions.
Within each family, the assembly languagesf r the individual microprocessors usually arc almost identical to one another. The rvpiral microprocessor has within it a set of registers, sometimes called general-purpose registers, each of which can hold a value that the processor is workmg wah.
Before doing any opera tion on data, such as arithmetic, tor ex. Each nucroproc. For this discussion, we will assume that our nur roproccssor has registers called Rl, R2, R3, and so on. In addition to the general-purpose registers. Every microprocessor has a program counter, which keeps track of the address of the next instruction that the microprocessor is to execute. Most have a stack pointer, w-hich stores the memory address of the top of the general purpose microprocessor stack.
In a typical assembly language, when the name of a variable appears in an instruction, that refers to the address of that variable. To refer to the value of a variable, yon put the name of the variable in parentheses. In most assembly languages anything that follows a semicolon IS a comment, and the assembler will ignore it. Note that this instruction. Although some microprocessors can only do arithmetic in a special register called the accumulator, many can do standard arithmetic or bit-oriented operations in any register.
For example. Assembly languages have ajump instruction that unconditionally continues execution at the instruction whose label matches the one found in the jump instruction.
Labels arc followed by colons in many assembly languages. Assembly languages also contain conditional jump instructions, instructions that jump if a certain condition is true.
Most microprocessors can test. In some assembly languages, this instruction would operate in the opposite direction, reading the value in register R3 and copying it into register R2. Assembly languages differ from one another in all sorts of details such as this. In this section we'll discuss what interrupts are, what microprocessors rvnically do when an interrupt happens, what interrupt routines typically do, and how they are usually written, Readers familiar with this material should skip to Section 4,3,.
Each of these chips has a pm that It asserts when it requires service. The hardware engineer attaches this pin to an input pin on the microprocessor called. An interrupt routine is sometimes called an interrupt handler. It is also sometimes called by the abbreviation [SR. When it gets there, the microprocessor retrieves from the stack the address of the next instruction it should do the one it was about to do when the interrupt occurred and resumes execution from there.
In effect, the interrupt routine acts like a subroutine that is called whenever the hardware asserts the interrupt request signal. There is no CALL instruction; the microprocessor does the call automatically in response to the hardware signal. Figure 4. On the lefthand side of this figure, the microprocessor is busy doing the task code, the term we will use in this book for any code that is not part of an interrupt routine.
There is no common word for this concept. The task code in Figure 4. It moves the centigrade temperature into register R 1. When the interrupt occurs, the microprocessor suspends the task code and goes to the instructions that make up the interrupt routine. It does all of those instructions; when it comes to the RETURN instruction at the end of the interrupt routine, it goes back to the task code and continues converting temperatures.
Most microprocessors have several such pins so that several different chips can be connected and request the microprocessor's attention. See Figure 4. When the microprocessor detects that a signal attached to one of its interrupt request pIllS is asserted, it stops executing the sequence of instructions it was executing, saves on the stack the address of the instruction that would have been next, and Jumps to an interrupt routine.
Interrupt routines are subroutines that you write.
For example, when the interrupt comes from the serial port chip and that chip has received a character from the serial port, the interrupt routine must read the character fr the serial port chip and put it into memory. Typically, interrupt routines also must do some miscellaneous housekeeping chores, such as resetting the interrupt-detecting hardware within the microprocessor to be ready for the next intcr rupt.
When you write interrupt routines for those microprocessors, you must use the special instruction. Notice that the task code in Figure 4.
If the centigrade temperature is 15, then the microprocessor will load 15 into register RI. Ifsoething changes the value in register Rl in the mean time, then the program won't convert the temperatures properly. It is therefore necessary that the value register Rl be the same after the interrupt routine finishes as it was before the interrupt routines started. It is difficult or impossible for a microprocessor to get much done without using at least some of the registers.
As we mentioned in Section 4. Therefore, it is unreasonable to expect anyone to write an interrupt routine that doesn't touch any of the registers. The most common practice to get around this problem is for the interrupt routine to save the contents of the registers it uses at the start of the routine and to restore those contents at the end.
Usually, the contents of the registers are saved on the stack. In Figure 4. Similarly, you must write your interrupt service routines to push and pop ill of the registers they use, since you have no way of knowing what registers will have important values in them when the interrupt occurs.
Pushing all of the registers at the beginning of an interrupt routine is known as saving the context; popping them at the end, as restoring the context. Failing to do these operations properly can cause troublesome bugs. For exampl e, if whoever wrote the interrupt routine in Figure 4.
The distressing thilig about this bug would be that temperatures might well be translated properly most of the time. The bug would only show up occasionally, when the interrupt just happened to occur in the middle of the calculation. As long as the interrupt occurred only when register Rl is not important, the system would appear to work just fine.
Almost every system allows YOll to disable interrupts, usually in a variety of ways. This stops the interrupt signal at the source. Further, most microprocessors allow your program to tell them to ignore incoming signals on their interrupt request pins. In most cases your program can select tbe individual interrupt request signals to which the microprocessor should pay attention and [hose it should Ignore, usually by writing a value in special register in the microprocessor.
Most microprocessors have a nonrnaskable interrupt, an input pin that causes an interrupt that cannot be disabled. As we will discuss in Section 4.
Because of this, the nonmaskable interrupt is most commonly used for events that are completely beyond the normal range of the ordinary processing. For example, you might usc it to allow your system to react to a power failure or a similar catastrophic event. Some microprocessors usc a somewhat different mechanism for disabling and enabling interrupts. These microprocessors assign a priority to each interrupt request signal and allow your program to specify the priority, of the lowestpriority interrupt that it is willing tohand1e at any given time, It can disable all interrupts except for the nonrnaskable interrupt by setting the acceptable priority higher than that of any interrupt, it can enable all-interrupts by setting the acceptable priority very low, and it can selectively enable interrupts in priority order by setting the acceptable priority at intermediate values.
This priority mechanism is sometimes in addition to allowing you to enable and disable individual interrupts. How does the microprocessor know where to jind the interrupt routine when the interrupt occurs?
This depends on the microprocessor, and you'll have to look at the manual to find out how your microprocessor does it. Some microprocessors assume that the interrupt service routine is at a fixed location. It becomes your job to make sure that the interrupt routine is there. Other microprocessors have more sophisticated methods. The most typical is that a table somewhere in memory contains interrupt vectors, the addresses of the interrupt routines.
When an interrupt occurs, the microprocessor will look up the address of the interrupt routine in this interrupt vector table. Again, it is your job to set up that table properly. HoUJ do microprocessors that Hse ilU interrupt vector table know where the table is? Again, this depends upon the microprocessor.
In others, the microprocessor provides your program with some way to tell it where the table is. Usually not.
In almost every case, the microprocessor will finish the instruction that it is working on before jumping to the interrupt routine. The most common exceptions are those single instructions that move a lot of data from place to place.
Both the Zilog Z80 and the Intel x86 families of microprocessors, for example, have single instructions that move potentially thousands of bytes of data. These instructions can be interrupted at the end of transferring a single byte or word and will resume where they left off when the interrupt routine returns. If two interrupt; happen at the same time, which interrupt routine does the microprocessor dojirst? Almost every microprocessor assigns a priority to each interrupt signal, and the microprocessor will do the interrupt routine associated with the higherpriority signal first.
Microprocessors vary all over the map when it comes to how your program can control the priorities of the interrupts. On most microprocessors, yes. On some microprocessors it is the default behavior; on others, you have to put an instruction or two into your interrupt routines to allow this interrupt nesting. The Intel x86 microprocessors, for example, disable all interrupts automatically whenever they enter any interrupt routine; therefore, the interrupt routines must reenable mterrupts to allow interrupt nesting.
Other processors do': In any case, a higher-priority interrupt can interrupt a lower-priority interrupt routine, but not the other way around. If the microprocessor is executing a higher-priority interrupt routine when the hardware asserts the lower-priority interrupt signal, the microprocessor will finish the higher-priority interrupt routine and then execute the lower-priority interrupt routine. What happens ifan interrupt is signaled while the interrupts are disabled?
In most cases the microprocessor will remember the interrupt until interrupts are reenabled, at which point it will jump to the interrupt routine. If more than one interrupt is signaled while interrupts are disabled, the microprocessor will do them in priority order when interrupts are reenabled. Interrupts, therefore, are not really disabled; they are merely deferred. The microprocessor will execute no more interrupt routines, and any processing in your system that depends upon interrupt routines-which is usually all processing in an embedded system-will grind to a halt.
Are interrupts enabled or disabled when the microprocessor first starts 14p? Can I write mv Lnterrupt routines in C? Yes, usually. Most compilers used for embedded-systems code recognize a nonstandard keyword that allows you to tell the compiler that a particular function is an interrupt routine.
The compiler will add code to vHandl eTi mer! RQ to save and restore the context. If yours is one of the microprocessors that requires a special assembly" language RETURN instruction for interrupt routines, the compiler will end, vHandleTi mer! RO with it. Your C code must deal with the hardware properlywhich is usually possible in C-and set up the interrupt vector table with the address of your routine-also usually possible in C.
The most common reason for writing interrupt routines in assembly language is that on many microprocessors you can write faster code in assembly language than you can in C.
If speed is not an issue, writing your interrupt routines in C is a good idea. One problem that arises as soon as you use interrupts is that your interrupt routine, need to communicate with the rest of your code.
For various reasons, some of which we will discuss III Section 4. Therefore", interrupt routines need to signal the task code to do follow-up processing. Suppose that the code Figure 4. In the code in FIgure 4. The interrupt routine, v Rea d Tempe rat u res, happens periodicallv: The interrupt routine reads the new temperatures. The idea is that the system will set off a howling alarm if the temperatures ever turn out to be ditTerent.
What IS the problem with the program in figure 4. It sets off the alarm when it shouldn't. To see why, suppose that both temperatures have been 73 degrees for a while; both elements of the i Tempe rat u re s array equal Suppose now that the microprocessor has just finished executing this line of code, setting i TempO to Suppose that the interrupt occurs now and that both temperatures have changed to 74 degrees.
The interrupt routine writes the value 74 into both elements of the iTemperatures array. When the interrupt routine ends, the microprocessor will continue with this line of code. Since borhclcmcnts of the array arc now 74, i Temp l will be set to Now examine Figure 4. The code in Figure 4,5 is the same as the code in Figure 4.
Reference Books: Embedded system design by Arnold S Burger. An Embedded Software Primer by Simon. Horowitz, Paul and Hill, Winfield. Upper Saddle River, NJ: Prentice Hall; Embedded systems: Architecture, programming and design by Rajkamal, TMH. Alles, was man wissen muss book. Architecture, Construction Contracts: Theory and Practice Computer Graphics: Insider Tips from The Java Tutorial: Zoologie pdf free Autopsy Pathology: A Manual and Atlas: